By: stefan peter (stefanpeter) Date: 2011-08-24 17:24 Subject: RE: Minimal Solution
Maybe I didn't make myself clear:
I have arbitrary propositional logic expressions over variables x_1, .. x_n, which I add to SAT4J using the gate translators.
Those gate translators introduces new variables y_1...y_m and those are the variables i meant by saying internal variables.
So is there a way of just iterating over the partial assignments of the variables x_1..x_n and disregarding y_1 .. .y_m ?
Start New Thread
